1. Field of the Invention
The present invention relates to a solid state imaging device including: a photoelectric conversion element including a pair of electrodes stacked over a semiconductor substrate and a photoelectric conversion layer sandwiched between the electrodes; and a signal output circuit for outputting a signal responsive to an electric charge generated by the photoelectric conversion layer.
2. Description of Related Art
JP-A-2005-268477 discloses a solid state imaging device including: a semiconductor substrate on which a signal reading circuit including an MOS transistor circuit is formed; a photoelectric conversion film which is stacked over the semiconductor substrate, and through which a signal electric charge responsive to an incident light amount is generated; a connection section which is provided at a surface of the semiconductor substrate, and to which wiring for guiding the signal electric charge to the surface of the semiconductor substrate is connected; a potential barrier means which is provided so as to be adjacent to the connection section, and serves as a constant potential barrier for an electric charge of the connection section; and an electric charge storage section which is provided so as to be adjacent to the potential barrier means, and is connected to a gate of an output transistor constituting the signal reading circuit.
In such a structure, a photoelectric charge generated by the photoelectric conversion film is allowed to smoothly flow to the gate of the output transistor, and in terms of the gate of the output transistor, an effective capacitance of a signal electric charge storing section is reduced, and a signal voltage is increased, thus making it possible to obtain a high-sensitivity output signal.
FIG. 17 is a diagram for describing how the solid state imaging device disclosed in JP-A-2005-268477 operates, in which there is shown a cross-sectional potential within a semiconductor substrate.
In order to obtain a signal from one pixel of the solid state imaging device, first, an electric charge stored in the electric charge storage section is discharged to a reset drain to trigger a reset (time T0). At this time, as shown in the diagram, a reset noise N1, which is a noise electric charge generated with a reset operation, is stored in the electric charge storage section. Upon completion of the reset, the light exposure of the photoelectric conversion film is started, and a signal electric charge Q, generated by this light exposure, is allowed to go through the potential barrier from the connection section, and is stored in the electric charge storage section (time T1). Then, a signal, responsive to an electric charge amount stored in the electric charge storage section during this light exposure period, is outputted from the signal reading circuit. After the signal has been outputted, a reset operation is performed again as indicated by a time T2, a reset noise N2 is stored in the electric charge storage section, and the next light exposure is started in this state.
A signal processing circuit for processing a signal outputted from the solid state imaging device includes a correlated double sampling (CDS) circuit for performing a correlated double sampling process on the signal. In this CDS circuit, sampling is performed on two types of signals, i.e., a signal responsive to a reset noise and a signal responsive to a signal electric charge including the reset noise, and a difference between both the signals is determined, thus removing the reset noise.
A signal responsive to the reset noise N1, which has been obtained at the time T0, is subtracted from an imaging signal obtained at the time T1, thereby making it possible to completely remove the reset noise. In order to perform such a process, it is necessary for the CDS circuit to perform sampling on a signal outputted from the solid state imaging device at the time T0 (sampling SP1), and sampling on a signal outputted from the solid state imaging device at the time T1 (sampling SP2) to determine a difference between both the signals. However, the time period from the sampling SP1 to the sampling SP2 is identical to the light exposure period, and the CDS circuit has to sequentially process signals from all pixels; therefore, if the signal sampling is performed at such a time interval, it becomes impossible for the processing to keep up with the signals outputted from the solid state imaging device.
Therefore, a signal subjected to sampling (sampling SP3) at the time T2 has conventionally been subtracted from a signal subjected to sampling at the time T1, thus removing the reset noise. Since the time interval between the sampling SP2 and the sampling SP3 is sufficiently shorter compared with the light exposure period, a CDS process can be performed on signals from all pixels without problems.
However, the reset noise generated by a reset operation is not constant but is varied; therefore, the reset noise cannot be properly removed by performing a process of subtracting the reset noise, generated by the reset operation at the time T2, from the signal including the reset noise generated by the reset operation at the time T0.